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Дата13.02.2017
Размер214.22 Kb.
#14905
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.

Found 1-bit register for signal .

Found 1-bit register for signal .

Found 11-bit comparator greater for signal created at line 52.

Found 10-bit up counter for signal .

Found 11-bit comparator greatequal for signal created at line 96.

Found 11-bit comparator lessequal for signal created at line 96.

Found 11-bit comparator greater for signal created at line 81.

Found 10-bit up counter for signal .

Found 11-bit comparator greatequal for signal created at line 100.

Found 11-bit comparator lessequal for signal created at line 100.

Summary:


inferred 2 Counter(s).

inferred 6 D-type flip-flop(s).

inferred 6 Comparator(s).

Unit synthesized.

=========================================================================

HDL Synthesis Report


Macro Statistics

# Counters : 2

10-bit up counter : 2

# Registers : 6

1-bit register : 6

# Comparators : 6

11-bit comparator greatequal : 2

11-bit comparator greater : 2

11-bit comparator lessequal : 2
=========================================================================
=========================================================================

* Advanced HDL Synthesis *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report
Macro Statistics

# Counters : 2

10-bit up counter : 2

# Registers : 6

Flip-Flops : 6

# Comparators : 6

11-bit comparator greatequal : 2

11-bit comparator greater : 2

11-bit comparator lessequal : 2
=========================================================================
=========================================================================

* Low Level Synthesis *

=========================================================================
Optimizing unit ...
Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block vga, actual ratio is 0.
Final Macro Processing ...
=========================================================================

Final Register Report


Macro Statistics

# Registers : 26

Flip-Flops : 26
=========================================================================
=========================================================================

* Partition Report *

=========================================================================
Partition Implementation Status

-------------------------------


No Partitions were found in this design.
-------------------------------
=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : vga.ngr

Top Level Output File Name : vga

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No
Design Statistics

# IOs : 29


Cell Usage :

# BELS : 118

# GND : 1

# INV : 2

# LUT1 : 18

# LUT2 : 32

# LUT3 : 2

# LUT4 : 18

# LUT4_D : 3

# LUT4_L : 3

# MUXCY : 18

# VCC : 1

# XORCY : 20

# FlipFlops/Latches : 26

# FDC : 15

# FDCE : 10

# FDR : 1

# Clock Buffers : 2

# BUFG : 1

# BUFGP : 1

# IO Buffers : 28

# IBUF : 4

# OBUF : 24

=========================================================================


Device utilization summary:

---------------------------


Selected Device : 3s500efg320-5
Number of Slices: 42 out of 4656 0%

Number of Slice Flip Flops: 23 out of 9312 0%

Number of 4 input LUTs: 78 out of 9312 0%

Number of IOs: 29

Number of bonded IOBs: 29 out of 232 12%

IOB Flip Flops: 3

Number of GCLKs: 2 out of 24 8%
---------------------------

Partition Resource Summary:

---------------------------
No Partitions were found in this design.
---------------------------

=========================================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 1 |

clk251 | BUFG | 25 |

-----------------------------------+------------------------+-------+


Asynchronous Control Signals Information:

----------------------------------------

-----------------------------------+------------------------+-------+

Control Signal | Buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

reset | IBUF | 25 |

-----------------------------------+------------------------+-------+
Timing Summary:

---------------

Speed Grade: -5
Minimum period: 4.672ns (Maximum Frequency: 214.064MHz)

Minimum input arrival time before clock: 1.731ns

Maximum output required time after clock: 7.771ns

Maximum combinational path delay: No path found


Timing Detail:

--------------

All values displayed in nanoseconds (ns)
=========================================================================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 1.689ns (frequency: 592.084MHz)

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------

Delay: 1.689ns (Levels of Logic = 0)

Source: clk25 (FF)

Destination: clk25 (FF)

Source Clock: clk rising

Destination Clock: clk rising


Data Path: clk25 to clk25

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDR:C->Q 2 0.514 0.380 clk25 (clk251)

FDR:R 0.795 clk25

----------------------------------------

Total 1.689ns (1.309ns logic, 0.380ns route)

(77.5% logic, 22.5% route)
=========================================================================

Timing constraint: Default period analysis for Clock 'clk251'

Clock period: 4.672ns (frequency: 214.064MHz)

Total number of paths / destination ports: 436 / 32

-------------------------------------------------------------------------

Delay: 4.672ns (Levels of Logic = 5)

Source: hcount_7 (FF)

Destination: hcount_9 (FF)

Source Clock: clk251 rising

Destination Clock: clk251 rising


Data Path: hcount_7 to hcount_9

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 14 0.514 1.002 hcount_7 (hcount_7)

LUT1:I0->O 1 0.612 0.000 Mcount_hcount_cy<7>_rt (Mcount_hcount_cy<7>_rt)

MUXCY:S->O 1 0.404 0.000 Mcount_hcount_cy<7> (Mcount_hcount_cy<7>)

MUXCY:CI->O 0 0.052 0.000 Mcount_hcount_cy<8> (Mcount_hcount_cy<8>)

XORCY:CI->O 1 0.699 0.509 Mcount_hcount_xor<9> (Result<9>)

LUT2:I0->O 1 0.612 0.000 Mcount_hcount_eqn_91 (Mcount_hcount_eqn_9)

FDC:D 0.268 hcount_9

----------------------------------------

Total 4.672ns (3.161ns logic, 1.511ns route)

(67.7% logic, 32.3% route)


=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk251'

Total number of paths / destination ports: 3 / 3

-------------------------------------------------------------------------

Offset: 1.731ns (Levels of Logic = 1)

Source: blue (PAD)

Destination: b (FF)

Destination Clock: clk251 rising


Data Path: blue to b

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 1.106 0.357 blue_IBUF (blue_IBUF)

FDC:D 0.268 b

----------------------------------------

Total 1.731ns (1.374ns logic, 0.357ns route)

(79.4% logic, 20.6% route)
=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk251'

Total number of paths / destination ports: 93 / 24

-------------------------------------------------------------------------

Offset: 7.771ns (Levels of Logic = 4)

Source: vcount_7 (FF)

Destination: row<8> (PAD)

Source Clock: clk251 rising


Data Path: vcount_7 to row<8>

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDCE:C->Q 5 0.514 0.690 vcount_7 (vcount_7)

LUT2:I0->O 2 0.612 0.410 row_cmp_gt00001_SW0 (N01)

LUT4:I2->O 8 0.612 0.795 row_cmp_gt00001 (row_cmp_gt0000)

LUT2:I0->O 1 0.612 0.357 row<8>1 (row_8_OBUF)

OBUF:I->O 3.169 row_8_OBUF (row<8>)

----------------------------------------

Total 7.771ns (5.519ns logic, 2.252ns route)

(71.0% logic, 29.0% route)


=========================================================================

Total REAL time to Xst completion: 5.00 secs

Total CPU time to Xst completion: 5.35 secs

-->
Total memory usage is 243736 kilobytes


Number of errors : 0 ( 0 filtered)

Number of warnings : 1 ( 0 filtered)



Number of infos : 0 ( 0 filtered)



ИЗПОЛЗВАНА ЛИТЕРАТУРА :
1.Communications:Interfacing to the PS/2 Keyboard
2.VGA RefComp.zip from www.digilentinc.com
3.4OI4 Engineering Design VGA Video Signal Generation - McMaster University
4. Digital Systems Design Video Signal Generation for the Altera DE2 Board -Lecture 11
5. A VGA Display Controller by Eduardo Sanchez





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